Product Highlights

Available at speeds ranging from 850 MHz to 1.80 GHz.
100 MHz multi-transaction processor system bus on Intel Celeron processors at
850 MHz to 1.40 GHz frequencies.
400 MHz multi-transaction processor system bus on Intel Celeron processors at
1.70 GHz to 1.80 GHz frequencies.
Dynamic Execution technology.
Includes Intel MMX™ media enhancement technology.
Intel Streaming SIMD Extensions.
Integrated Level 1 cache.
Integrated Level 2 cache.
Intel Chipset support is determined by processor frequency. Please refer to the
value platform web site for assistance.
Fully compatible with existing Intel Architecture-based software.

Intel's Streaming SIMD Extensions

The Internet Streaming SIMD Extensions consist of 70 instructions and includes single
instruction, multiple data for floating-point, additional SIMD-integer and Cacheability
control instructions. Some of the benefits to desktop and Internet applications of Internet
Streaming SIMD Extensions include:

Higher resolution and quality images can be viewed and manipulated than
previously possible.
High quality audio, MPEG2 video, and simultaneous MPEG2 encoding and
decoding.
Reduced CPU utilization for speech recognition, as well as higher accuracy and
faster response times.
Streaming SIMD Extensions 2 (SSE2) instructions.

High Performance Intel® MMX™ Technology

Intel MMX technology includes instructions and data types that allow applications to
achieve a new level of performance. Intel's MMX technology is designed as a set of
basic, general-purpose integer instructions that are easily applied to the needs of a wide
diversity of multimedia and communications applications.

The highlights of the technology are:

Single Instruction, Multiple Data (SIMD) technique
57 new instructions
Eight 64-bit wide Intel MMX™ technology registers
Four new data types

Non-Blocking Level 1 Cache

The Intel Celeron processor includes two separate 16 KB level 1 (L1) caches, one for
instruction and one for data. The L1 cache provides fast access to the recently used data,
increasing the overall performance of the system.

Level 2 Advanced Transfer Cache

The Advanced Transfer Cache (ATC) consists of microarchitectural improvements to
provide a higher data bandwidth interface between the level 2 cache and the processor
core that is completely scaleable with the processor core frequency.

Features of the ATC include:

Non-Blocking, full speed, on-die level 2 cache
Reduced latency interface to cache data (as compared to discrete caches)

Non-Blocking Level 2 Cache

A Discrete, off-die level 2 (L2) cache. This L2 cache consists of a unified, non-blocking
cache that improves performance over cache-on-motherboard solutions by reducing the
average memory access time and by providing fast access to recently used instructions
and data. Performance is also enhanced over cache-on-motherboard implementations
through a dedicated 64-bit cache bus.

Other Significant Features

Intel Celeron processors are available in the Flip-Chip Pin Grid Array (FC-PGA)
and the Flip-Chip Pin Grid Array 2 (FC-PGA2) package with an Integrated Heat
Spreader (see Figure 1 above).
100 MHz system bus for the Intel Celeron processors from 850 MHz to 1.40
GHz.
400 MHz system bus for the Intel Celeron processor at 1.70 GHz to 1.80 GHz.
A pipelined Floating-Point Unit (FPU) for supporting the 32-bit and 64-bit
formats specified in IEEE standard 754, as well as an 80-bit format.
Parity-protected address/request and response system bus signals with a retry
mechanism for high data integrity and reliability.

Testing and Performance Monitoring Features

Built-in Self Test (BIST), provides single stuck-at fault coverage of the microcode
and large PLAs, as well as testing of the instruction cache, data cache, Translation
Lookaside Buffers (TLBs) and ROMs.
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture
mechanism, allows testing of the Intel Celeron processor through a standard
interface.
Internal performance counters can be used for performance monitoring and event
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